等离子体点火器中PFN能量存储体积减小

等离子体点火器中PFN能量存储体积减小

抽象

A pulse-forming network holds the ignition charge and releases it with the waveform the torch needs, and it occupies volume that portable cutters and robot-mounted torches do not have. This article gives the energy-density equations, the dielectric comparison that removes 56 % of the active volume, the inductance and rise-time constraint, four miniaturization traps, six design steps and the thermal arithmetic.

1. 引言

Every plasma cutting igniter carries a pulse-forming network: the energy storage and shaping unit that holds the charge for the ignition pulse and releases it with the waveform the torch needs.

Traditional networks use wound film capacitors, chunky inductors and generous spacing for creepage. Together they take a large share of the enclosure, and the market is moving toward compact machines that mount the torch directly on a robot arm.

The engineering tension is real. Pulse energy follows E = ½CV², so shrinking the capacitor at constant energy needs either a higher voltage, which complicates insulation and creepage, or a higher energy density in the dielectric.

This article gives the energy-density arithmetic, the dielectric comparison, the inductance constraint that keeps the pulse shape, the thermal limit that decides how small the part can get, and the six steps that hold pulse fidelity at reduced volume.

2. 核心机制

2.1 Energy in the dielectric

The network stores ignition energy as electrostatic field energy, and the field energy depends on the dielectric and the volume it occupies.

E = ½ ε₀ ε_r E_max² V_diel

where E is the stored energy in joules, ε₀ stands for the permittivity of free space, 8.854 × 10⁻¹² F/m, ε_r is the relative permittivity, E_max is the peak electric field in volts per metre, and V_diel covers the active dielectric volume in cubic metres. Two levers follow: raise the permittivity, or raise the field the dielectric tolerates.

2.2 Energy density and the dielectric comparison

Dividing by volume gives the number that decides how much space a given pulse energy needs.

w = E / V_diel = ½ ε₀ ε_r E_max²

where w is the volumetric energy density in joules per cubic metre. A SrTiO3 Class I dielectric at ε_r = 2000 and 10 MV/m reaches 0.885 J/cm³, and a BOPP film at ε_r = 2.2 and 200 MV/m reaches 0.390 J/cm³. For the 235 mJ that a 4.7 nF tank holds at 10 kV, the ceramic needs 0.27 cm³ of active dielectric and the film needs 0.60 cm³, so the ceramic removes 56 % of the active volume.

The comparison holds only at the rated field. A high-permittivity Class II ceramic collapses under DC bias, losing 30–70 % of its rated capacitance at rated voltage, which erases the volume advantage and distorts the pulse envelope at the same time.

2.3 Pulse shape and the inductance floor

Pulse fidelity depends on the loop inductance and the capacitance together, because they set the rise time.

t_r ≈ 2.2 √(L C)

where t_r is the 10–90 % rise time of the pulse, L is the total loop inductance, and C is the network capacitance. The rise time also has a floor set by the part itself: a capacitor rated above 50 kV/µs at 10 kV needs at least 200 ns to reach rated voltage, and a design margin of two puts the target at 400 ns.

Solving the rise relation for that target with a 4.7 nF capacitor gives a loop inductance of 7.0 µH, which is series inductance that the design adds. The parasitic part of the loop, meaning the capacitor ESL plus the interconnect, then has to stay small against it. A 2 % allowance sets a parasitic limit of 140 nH, and the resulting loop presents 38.7 Ω of characteristic impedance and 259 A of peak current at 25 kV/µs.

2.4 The thermal limit on small bodies

Every ignition event loses a fraction of the stored energy in the dielectric, and the loss per resonant cycle follows the loss factor.

E_loss = 2π tanδ E

where E_loss is the energy lost per cycle, tanδ is the loss factor, and E is the stored energy. A Class I part at tanδ = 0.1 % loses 1.48 mJ per event out of 235 mJ, and a Class II part at 2 % loses 29.5 mJ.

ΔT = P_loss R_th

where ΔT is the body temperature rise, P_loss is the average dissipation, and R_th is the thermal resistance from the body to the surroundings. At 100 events per second and 60 K/W, the Class I part runs 8.9 K above ambient and the Class II part runs 177 K above it. Shrinking the body raises R_th, so volume reduction and loss reduction belong in the same decision.

Fig. 1 — The same 235 mJ of ignition energy needs 0.60 cm³ of BOPP film dielectric and 0.27 cm³ of SrTiO3 Class I dielectric.

3. 工程痛点

Pain Point 1: Capacitance collapse under DC bias

Compact Class II ceramics lose 30–70 % of their rated capacitance at rated DC voltage. The network then holds far less energy than the label promises, designers oversize the capacitor to compensate, and the miniaturization gain disappears along with the accuracy of the pulse math.

Pain Point 2: Parasitic inductance growth from cramming

When capacitors, busbars and switches are packed together the current loop is often routed around other parts, which adds 50–150 nH. The rise time stretches, the overshoot changes, and the ignition timing moves away from the design point.

Pain Point 3: Thermal concentration in a small body

A small body with high stored energy concentrates loss into little mass and a higher thermal resistance. The body temperature rises, loss rises further in any lossy dielectric, and the failure arrives weeks after installation with no external warning.

Pain Point 4: Creepage and partial discharge in tight spaces

Shrinking the network shrinks the creepage between high-voltage nodes, and partial discharge starts at 60–80 % of rated voltage once the spacing drops below the design value. Sustained discharge erodes the insulation, and the eventual failure is unpredictable.

4. 设计步骤

Strategy 1: Choose the dielectric on energy density at the rated field

Compare candidate materials on w = ½ε₀ε_r E_max² at the field the part actually holds, and verify the capacitance at rated DC bias and at the operating temperature. A datasheet value taken at zero bias says nothing about either.

Strategy 2: Set the inductance allowance on the parasitic part

Fix the series inductance from the required rise time, then allow at most 2 % of it for capacitor ESL and interconnect. For a 7.0 µH loop that means 140 nH, which is a layout specification and not a component specification.

Strategy 3: Design the thermal path with the electrical one

Provide a low-resistance thermal path from the capacitor bodies to the enclosure or a spreader plate, and confirm from the measured loss per pulse that the steady-state body temperature stays below the derating point of the dielectric.

Strategy 4: Verify partial discharge in the compacted assembly

Test the finished network at 120 % of the maximum ignition voltage inside the real enclosure, and require PD below 5 pC per component. Creepage that works on the bench can fail once the potting compound and the enclosure are in place.

Strategy 5: Simulate the envelope on extracted parasitics

Build a model with the measured C, ESL and ESR of every component plus the extracted loop inductance, and confirm the rise time and the overshoot stay inside the ignition window before any hardware is cut. A 薄膜电容器 choice changes both terms at once.

Strategy 6: Build a modular cell from parallel capacitors

Assemble the energy unit from smaller parallel parts instead of one large part. Thermal distribution improves, the parallel paths lower ESL, and the same cell can be scaled from a portable machine to a heavy-plate system.

组件参数	典型值	测试条件
额定电压（HVCT8G系列）	10 kV DC	高压1.5倍，持续60秒
电容量	4700 pF ±20% (472M)	1 MHz，1 V rms
1 MHz 下的 ESR	低于 50 mΩ	25°C
回路电感（E40弦）	低于 8 nH	端子间距 40 毫米
绝缘电阻	500V直流电压下电阻大于10GΩ	25℃，60%相对湿度
温度范围	−40 °C 至 +125 °C	IEC 60068-2系列
脉冲dv/dt能力	高于 50 kV/µs	额定电压

5. HVC capacitors for compact pulse-forming networks

Three properties decide how much volume a network can shed: energy density at the rated field, loss per pulse and parasitic inductance. HVC builds N4700 parts for all three.

这里需要考虑的六个参数

• A SrTiO3 Class I dielectric at ε_r 2000 delivers high energy density at the rated bias without the collapse that Class II materials show.
• tanδ at or below 0.1 % holds the loss per event at 1.48 mJ out of 235 mJ, so a small body stays inside its thermal limit at 100 events per second.
• ±30 ppm/°C holds capacitance steady, so the network's impedance and rise time do not drift with warm-up or duty cycle.
• PD below 5 pC supports aggressive creepage reduction, because the dielectric itself does not discharge at compact spacings.
• 此 HVCT8G screw-terminal and radial-lead packages keep internal paths short, which holds the parasitic inductance inside the 140 nH allowance.
• 现场记录：在高压现场服务项目中，HVC 40 kV / 441 螺钉式电容器替代了国际一流部件，并且其结构与电气参数相匹配。 交叉参照 候选人。

交付和支持

标准部件的交货期为 4-8 周，配套组件的交货期为 6-10 周。1 kV 以上的设备可作为串联组件提供，并配有配套组件。 分级电阻器 以及夹紧 快速恢复二极管.

Send the required pulse energy, rise time, repetition rate and enclosure volume. HVC returns a network capacitor recommendation with measured energy density, ESL, ESR and PD data for that operating point.

6. 常见问题

Q1: What sets the energy density of a capacitor dielectric?

w = ½ε₀ε_r E_max². Permittivity and permissible field both enter, so a material with high ε_r at a modest field can beat one with low ε_r at a high field.

Q2: How much volume does a Class I ceramic save over film?

For 235 mJ at 10 kV, a SrTiO3 Class I part needs 0.27 cm³ of active dielectric against 0.60 cm³ for BOPP film at 200 MV/m, which is 56 % less.

Q3: Can a smaller network simply use a higher field?

Up to the partial-discharge limit. Discharge starts at 60–80 % of rated voltage once creepage drops below the design value, so the field and the spacing have to be designed together.

Q4: How much inductance is allowed in the loop?

Whatever the rise time needs, plus 2 % for parasitics. A 400 ns rise with 4.7 nF needs 7.0 µH of series inductance, which allows 140 nH of capacitor ESL and interconnect.

Q5: Why does the part heat up in a small body?

Loss per cycle runs at 2π tanδ times the stored energy, and a small body has both less mass and a higher thermal resistance. At 100 events per second the difference between 0.1 % and 2 % loss is 8.9 K against 177 K.

Q6: Why build the cell from parallel capacitors?

Parallel parts spread the heat, lower the effective ESL, and let one cell design scale from a portable cutter to a heavy-plate machine without a new qualification.

7。 参考

1. E. Kuffel、WS Zaengl、J. Kuffel 高电压工程基础知识，第 2 版，Newnes，2000 年。
2. N. Mohan、TM Undeland、WP Robbins 电力电子学：变换器、应用和设计，第 3 版，Wiley，2003 年。
3. MIL-HDBK-217F 通知 2， 电子设备可靠性预测1995。
4. IEC 60384-1:2021， 电子设备用固定电容器 - 第 1 部分：通用规范，第 6 版。日内瓦：IEC，2021 年。
5. IEC 61071:2017， 电力电子电容器，第 2 版。日内瓦：IEC，2017 年。
6. GB/T 17702-2021， 电力电子电容器。 北京: 中国标准出版社, 2021.
7. Y. Zhou、B. Chen、C. Tian、J. Yuan 和 Y. Chen， 用于电气设备耐压试验和局部放电测量的并联二​​极管钳位线性变换器，高电压，第 8 卷，第 1 期，第 171-182 页，2023 年。https://doi.org/10.1049/hve2.12312。
8. L. 郑、L. 朱、J. 刘、Z. 迪和 S. 吉， 金属化薄膜电容器在直流和交流叠加电压及谐波下的自愈特性，发表于 2022 年 IEEE 电气绝缘和介电现象会议 (CEIDP)，第 175-178 页，2022 年。https://doi.org/10.1109/ceidp55452.2022.9985286。
9. MKP金属化薄膜脉冲电容器——产品亮点KEMET Electronics，https://www.digikey.com/en/product-highlight/k/kemet/mkp-metallized-film-pulse-capacitors。
10. 美国 4,521,889, 用于储能的微带电容器，Kraftwerk Union AG，1985 年，https://www.osti.gov/biblio/6349373。
11. HVC应用工程团队 高压陶瓷电容器 技术资源https://www.hv-caps.com